full adder
英 [fʊl ˈædə(r)]
美 [fʊl ˈædər]
全加（法）器
双语例句
- Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic.
二进制加减，全加器的实现和性能，高速加法，带符号加法。 - Design methods of one-bit full adder circuit
一位全加器实验电路设计方法的研究 - Generalized Full Adder in Array Multiplier Design Model Application
一般化全加器在阵列乘法器设计中的典型应用 - A Dynamic Full Adder Circuit Based on Single Electron Transistors
基于单电子晶体管的动态全加器电路设计 - Alter the full adder cell from NMOS circuit to CMOS circuit. Basing on it, the paper introduces the design flow of converting NMOS circuit into CMOS circuit and some questions of the design.
将其中的全加器单元NMOS电路改为CMOS电路，本文以此为例，介绍了将NMOS电路改为CMOS电路时，建立CMOS单元库的流程及应注意的问题。 - Optoelectronic Interconnection Implementation for Binary Full Adder
二进制全加器的光电互连实现 - Based on logic gates of complementary single-electron transistor ( SET), three units are proposed as follows: full adder, shift register and ROM.
基于互补型单电子晶体管（SET）逻辑门，提出了SET加法器、移位寄存器和ROM的单元电路。 - Design of a Novel Full Adder Architecture
一种新型全加器结构的设计 - A Novel Full Adder Implementation Using Quantum Cellular Automata
基于量子细胞自动机的全加器实现 - A High Speed Unit of Full Adder
一种高速全加器运算单元 - A Novel Design of Full Adder
一种新的全加器设计方案 - A new PRNs digital full adder algorithm and its implementation scheme
一种新的PRNS数母全加器算法及其实现方案 - Design and test of a high speed PRNs digital full adder
高速PRNS数母全加器的设计及测试原则 - Using Full Adder to Design Code Conversion Circuit Xiong
利用集成全加器设计码制转换电路 - Full Adder Design and Comparision
全加器的设计及比较 - Optical full adder composed of a ZnS interference filter
用ZnS干涉滤光片构成的光学全加器 - Realization of a High Performances CMOS Full-Adder
高性能CMOS全加器设计 - Optical full adder composed of two optical bistable devices
用两个双稳器件构成的光学全加器 - A novel full adder has been designed. Compared with previous architecture, the new design is better both on speed and area.
加法器几乎在各种电路中都有着广泛的应用，提出了一种新的全加器结构，并相对于传统全加器，从面积和速度两方面论述了这种新结构的优点。 - In this paper, we present a polarization-encoded optical full adder by using an inverse vector realized by transmissive feedback.
提出了利用反转矢量透射反馈算法研制偏振编码光电混合全加器。 - Integrated Circuit Design for High Performance Low Power Quasi-Pseudo-NMOS/ DT-CPL-TG Full Adder
集成式高性能低功耗Quasi-Pseudo-NMOS/DT-CPL-TG全加器电路设计 - A model of algorithm has been proposed for composite neural network and the classification results of high precision are obtained through a full adder ( FA) fostered by the model.
提出了一种复合神经网络的算法模型，用该模型训练全加器（FA）获得了高精度分类结果。 - A 2 ∶ 1 multiplexer with base-0 signals and full adder with base-1 signals are illustrated and simulated. From the SPICE simulation results, the effectiveness of the proposed approach and the low power characteristic of the designed circuits are validated.
通过对基0信号2∶1数据选择器和基1信号全加器的设计及SPICE模拟，验证了所提出设计技术的有效性以及电路的低功耗特性。 - Secondly, circuits designing based on the MCML/ TG structure in the Post algebraic system and Mode algebraic system is proposed; then using the designed 3-T operator, the paper proposes one kind of full adder.
随后，基于该混合结构，论文设计了三值Post代数系统及模代数系统中的各基本电路，并应用所设计的T算子进行全加器的设计。 - In addition, among these widely used operations, subtraction and multiplication are most commonly applied. The 1-bit full adder is the building block of these operation modules.
在这些广泛应用的运算中，减法和乘法运用的更多，而加法器是组成这些运算的基本单元。 - Functional testing of a FPGA is investigated by implementing a full adder in it.
以一位全加器为例，研究了器件的功能测试方法。 - Later, by encoding the propagating waves and structural adjustments we designed a full binary adder unit, and verified it through simulation. The unit can well be extended in plane, and coupled together to realize a two-bit, or even multi-bit binary adder.
之后通过对脉冲进行编码，再设计合理的通道结构，我们给出并仿真验证了化学二进制加法器单元，该单元可以很好的在平面结构中进行扩展，进而实现两位甚至多位二进制加法器。 - First, the static adder, transmision function adder and static Energy-Recovery full adder are realized in the subthreshold circuit.
首先，进行了静态加法器、传输功能加法器和静态能量恢复加法器的亚阈值电路实现。